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infineon technologies 2002.01.25 hys64v64220gbdl 144 pin eight byte small outline dual-in-line synchronous dram modules for notebook applications two bank 64m x 64 non-parity module organisation suitable for use in pc100 and pc133 applications performance: single +3.3v( 0.3v ) power supply programmable cas latency, burst length and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh decoupling capacitors mounted on substrate all inputs, outputs are lvttl compatible serial presence detect with e 2 prom uses boc (?board-on-chip?) technique with 256mbit sdram (32mx8) chips. 8196 refresh cycles every 64 ms gold contact pad, jedec mo-190 outline dimensions this module family is fully pin and functional compatible with the latest intel so-dimm specification importante notice : this so-dimm module is based on 256mbit sdram technology and can be used in applications only, where 256mbit addressing is supported. -7.5 -8 pc133 3-3-3 pc100 2-2-2 units f ck clock frequency (max.) 133 100 mhz t ac clock access time cas latency = 2 & 3 5.4 6 ns 1 144 pin so-dimm sdram modules 512 mb pc100 / pc133
hy s 64v64220 g bdl 144 pin so-dimm sdram modules infineon technologies 2 2002.01.25 this infineon module is an industry standard 144 pin 8-byte synchronous dram (sdram) small outline dual in-line memory modules (so-dimm) which is organised as 64mx64 high speed array in two memory banks designed for use in non-parity applications. these so-dimms use boc (?board-on-chip?) technology. decoupling capacitors are mounted on the board. all boc package based so-dimm modules have a mechanical protection shield. the dimms use serial presence detects implemented via a serial e 2 promusingthetwopini 2 c protocol. the first 128 bytes are utilized by the dimm manufacturer and the second 128 bytes are available to the end user. all infineon 144-pin so-dimms provide a high performance, flexible 8-byte interface in a 67,6 mm long footprint. product spectrum note: all partnumbers end with a place code (not shown), designating the die revision. consult factory for current revision. example: hys64v64220gbdl-8-c2, indicating rev.c2 dies are used for sdram components. card dimensions pin names sdrams used rowaddr. bank select column addr. refresh period 64m x 64 hys64v64220gbdl-7.5 16 32mx8 13 ba0, ba1 10 8k 64 ms 64m x 64 hys64v64220gbdl-8 16 32mx8 13 ba0, ba1 10 8k 64 ms organisation pcb-board l x h x t [mm] 64m x 64 l-dim-144-12 67.60 x 29.21 x 3.80 a0-a12 address inputs ba0,ba1 bank selects dq0 - dq63 data input/output ras row address strobe cas column address strobe we read / write input cke0, cke1 clock enable clk0, clk1 clock input dqmb0 - dqmb7 data mask cs0 ,cs1 chip select vdd power (+3.3 volt) vss ground scl clock for presence detect sda serial data out for presence detect n.c. no connection
hys64v64220gbdl 144 pin so-dimm sdram modules infineon technologies 3 2002.01.25 pin configuration pin # front side pin # back side pin # front side pin # back side 1vss 2vss 73nc 74clk1 3dq0 4dq32 75vss 76vss 5dq1 6dq33 77nc 78nc 7dq2 8dq34 79nc 80nc 9 dq3 10 dq35 81 vdd 82 vdd 11 vdd 12 vdd 83 dq16 84 dq48 13dq4 14dq36 85dq17 86dq49 15dq5 16dq37 87dq18 88dq50 17dq6 18dq38 89dq19 90dq51 19dq7 20dq39 91vss 92vss 21 vss 22 vss 93 dq20 94 dq52 23 dqmb0 24 dqmb4 95 dq21 96 dq53 25 dqmb1 26 dqmb5 97 dq22 98 dq54 27 vdd 28 vdd 99 dq23 100 dq55 29 a0 30 a3 101 vdd 102 vdd 31 a1 32 a4 103 a6 104 a7 33 a2 34 a5 105 a8 106 ba0 35 vss 36 vss 107 vss 108 vss 37 dq8 38 dq40 109 a9 110 ba1 39 dq9 40 dq41 111 a10 112 a11 41 dq10 42 dq42 113 vdd 114 vdd 43 dq11 44 dq43 115 dqmb2 116 dqmb6 45 vdd 46 vdd 117 dqmb3 118 dqmb7 47 dq12 48 dq44 119 vss 120 vss 49 dq13 50 dq45 121 dq24 122 dq56 51 dq14 52 dq46 123 dq25 124 dq57 53 dq15 54 dq47 125 dq26 126 dq58 55 vss 56 vss 127 dq27 128 dq59 57 nc 58 nc 129 vdd 130 vdd 59 nc 60 nc 131 dq28 132 dq60 61 clk0 62 cke0 133 dq29 134 dq61 63 vdd 64 vdd 135 dq30 136 dq62 65 ras 66 cas 137 dq31 138 dq63 67 we 68 cke1 139 vss 140 vss 69 cs0 70 a12 141 sda 142 scl 71 cs1 72 (a13) 143 vdd 144 vdd
hy s 64v64220 g bdl 144 pin so-dimm sdram modules infineon technologies 4 2002.01.25 block diagram for two bank 64m x 64 sdram dimm - module dqm dq0-dq7 d0 cs dqm dq0-dq7 cs dqm dq0-dq7 dqm dq0-dq7 d1 cs1 cs0 dqmb0 dq(7:0) dqmb1 dq(15:8) dqmb2 dq(23:16) dqmb3 dq(31:24) a0-a12,ba0,ba1 vdd vss d0 - d7 c d0 - d7 d0 - d7 d0 - d7 d0 - d3 ras ,cas ,we cke0 dqm dq0-dq7 d4 cs dqm dq0-dq7 cs dqm dq0-dq7 dqm dq0-dq7 d5 dqm dq0-dq7 d2 cs dqm dq0-dq7 cs dqm dq0-dq7 dqm dq0-dq7 d3 dqmb4 dq(39:32) dqmb5 dq(47:40) dqmb6 dq(55:48) dqmb7 dq(63:56) dqm dq0-dq7 d6 cs dqm dq0-dq7 cs dqm dq0-dq7 dqm dq0-dq7 d7 d4 - d7 cke1 e 2 prom (256wordx8bit) scl sda sa0 sa1 sa2 note: 1. dq wiring may differ from the description in this drawing, however dq/dqmb/cke/cs relationship is maintained as shown. 2. in this design each of the d0 - d7 components are represented by two 32m x 8 chips. these two chips effectively work as a single 32m x 16 device. 8 loads clk0 clk1 8 loads 3. all resistors are 10 ohm.
hys64v64220gbdl 144 pin so-dimm sdram modules infineon technologies 5 2002.01.25 absolute maximum ratings dc characteristics t a =0to70 c; v ss =0v; v dd =3.3v 0.3 v capacitance t a =0to70 c; v dd =3.3v 0.3 v, f =1mhz parameter symbol limit values unit min. max. input / output voltage relative to v ss v in, v out ?1.0 4.6 v power supply voltage on v dd v dd ?1.0 4.6 v storage temperature range t stg -55 +125 o c power dissipation p d ?16w data out current (short circuit) i os ?50ma permanent device damage may occur if ?absolute maximum ratings? are exceeded. functional operation should be restricted to recommended operation conditions. exposure to higher than recommended voltage for extended periods of time affect device reliability parameter symbol limit values unit min. max. input high voltage v i h 2.0 vdd+0.3 v input low voltage v i l ?0.5 0.8 v output high voltage ( i out =?4.0ma) v oh 2.4 ? v output low voltage ( i out =4.0ma) v ol ?0.4v input leakage current, any input (0 v < v i n < 3.6 v, all other inputs = 0 v) i i (l) ?20 20 a output leakage current (dq is disabled, 0 v < v out < v dd ) i o(l) ?20 20 a parameter symbol limit values unit 64m x 64 max. input capacitance (a0 to a11, ba0, ba1) c i 1 85 pf input capacitance (ras ,cas ,we ) c i 2 85 pf input capacitance (clk0, clk1) c i 3 70 pf input capacitance (cs0, cs1) c i 4 60 pf input capacitance (dqmb0-dqmb7) c i 5 15 pf input capacitance (cke0, cke1) c i 6 50 pf input / output capacitance (dq0-dq63) c i o 18 pf input capacitance (scl,sa0-2) c sc 8pf input/output capacitance (sda) c sd 10 pf
hy s 64v64220 g bdl 144 pin so-dimm sdram modules infineon technologies 6 2002.01.25 operating currents per memory bank (t a =0to70 o c, v dd =3.3v 0.3v) (recommended operating conditions unless otherwise noted) parameter & test condition symb. 64mx64 512mbyte note pc133 pc100 operating current trc=trcmin., all banks operated in random access, all banks operated in ping-pong manner icc1 1840 1360 ma 1, 2 precharge standby current in power down mode cs =vih (min.), cke<=vil(max) tck = min. icc2p 16 16 ma 1 precharge standby current in non-power down mode cs = vih (min.), cke>=vih(min) tck = min. icc2n 320 240 ma 1 no operating current tck = min., cs = vih(min), active state ( max. 4 banks) cke>=vih(min.) icc3n 400 360 ma 1 cke<=vil(max.) icc3p 80 80 ma 1 burst operating current tck = min., read command cycling icc4 1200 800 ma 1, 2 auto refresh current tck = min., trc = trcmin. auto refresh command cycling icc5 1920 1760 ma 1 self refresh current self refresh mode, cke=0.2v tck =infinity icc6 14 14 ma 1 notes: 1. these parameters depend on the cycle rate. these values are measured at 133 mhz operation frequency for pc133 and at 100mhz for pc100 modules. input signals are changed once during tck, excepts for icc6 and for standby currents when tck=infinity. 2. these parameters are measured with continuous data stream during read access and all dq toggling. cl=3 and bl=4 is assumed and the data-out current is excluded.
hys64v64220gbdl 144 pin so-dimm sdram modules infineon technologies 7 2002.01.25 ac characteristics 1)2) t a =0to70 c; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit -7.5 pc133-333 -8 pc100-222 min. max. min. max. clock and access time clock cycle time cas latency = 3 cas latency = 2 t ck 7.5 10 ? ? 10 10 ? ? ns ns clock frequency cas latency = 3 cas latency = 2 t ck ? ? 133 100 ? ? 100 100 mhz mhz access time from clock cas latency = 3 cas latency = 2 t ac ? ? 5.4 6 ? ? 6 6 ns ns 2, 3 clock high pulse width t ch 2.5 ? 3 ? ns clock low pulse width t cl 2.5 ? 3 ? ns transition time t t 0.3 1.2 0.5 10 ns setup and hold parameters input setup time t is 1.5 ? 2 ? ns 4 input hold time t ih 0.8 ? 1 ? ns 4 power down mode entry time t sb ?1?1clk 4 power down mode exit setup time t pde 1?1?clk 4 mode register set-up time t rsc 2?2?clk common parameters row to column delay time t rcd 20?20?ns 5 row precharge time t rp 20?20?ns 5 row active time t ras 45 100k 50 100k ns 5 row cycle time t rc 67?70 ? ns 5 activate(a) to activate(b) command period t rrd 15?16?ns 5 cas (a) to cas (b) command period t ccd 1?1?clk
hy s 64v64220 g bdl 144 pin so-dimm sdram modules infineon technologies 8 2002.01.25 refresh cycle refresh period (8192 cycles) t ref ?64?64ms self refresh exit time t srex 1?1?clk 6 read cycle data out hold time t oh 3?3?ns data out to low impedance time t lz 0?0?ns data out to high impedance time t hz 3738ns 7 dqm data out disable latency t dqz ?2?2clk write cycle data input to precharge (write recovery) t wr 2?2?clk dqm write mask latency t dqw 0?0?clk parameter symbol limit values unit -7.5 pc133-333 -8 pc100-222 min. max. min. max.
hys64v64220gbdl 144 pin so-dimm sdram modules infineon technologies 9 2002.01.25 notes: 1. all ac characteristics shown are for sdram components. an initial pause of 100 s is required after power-up, then a precharge all banks command must be given followed by 8 auto refresh (cbr) cycles before the mode register set operation can begin. 2. ac timing tests have v il =0.4vandv ih = 2.4 v with the timing referenced to the 1.4 v crossover point.thetransitiontimeismeasuredbetweenv ih and v il . all ac measurements assume t t =1ns with the ac output load circuit shown.specified tac and toh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v / ns edge rate between 0.8v and 2.0 v. 3. if clock rising time is longer than 1ns, a time (t t -0.5) ns has to be added to this parameter. 4. if t t is longer than 1ns, a time (t t -1) ns has to be added to this parameter. 5. any time that the refresh period has been exceeded, a minimum of two auto (crb) refresh commands must be given to ?wake-up? the device. 6. self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to trc is satisfied once the self refresh exit command is registered. 7. referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 50 pf i/o measurement conditions for tac and toh clock 2.4 v 0.4 v input is t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t ih t 1.4 v io.vsd
hy s 64v64220 g bdl 144 pin so-dimm sdram modules infineon technologies 10 2002.01.25 serial presence detects a serial presence detect storage device - e 2 prom - is assembled onto the module. information about the module configuration, speed, etc. is written into the e 2 prom device during module production using a serial presence detect protocol ( i 2 c synchronous 2-wire bus) spd-table: byte# description spd entry value hex 64mx64 -7.5 64mx64 -8 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs) 12 0d 4 number of column addresses 10 0a 5 number of dimm banks 2 02 6 module data width 64 40 7 module data width (cont?d) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl=3 10.0 ns 75 a0 10 sdram access time from clock at cl=3 6.0 ns 54 60 11 dimm config (error det/corr.) none 00 12 refresh rate/type self-refresh, 7,6 s82 13 sdram width, primary x8 08 14 error checking sdram data width n/a 00 15 minimum clock delay for back-to- back random column address t ccd =1clk 01 16 burst length supported 1, 2, 4 & 8 0f 17 number of sdram banks 2 04 18 supported cas latencies 2, & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes non buffered/non reg. 00 22 sdram device attributes :general vdd tol +/- 10% 0e 23 sdram cycle time at cl = 2 10.0 ns a0 24 sdram access time from clock at cl=2 6.0 ns 60 25 sdram cycle time at cl = 1 not supported ff 26 sdram access time from clock at cl=1 not supported ff 27 minimum row precharge time 20 ns 14
hys64v64220gbdl 144 pin so-dimm sdram modules infineon technologies 11 2002.01.25 spd-table (cont?d): byte# description spd entry value hex hex 64mx64 -7.5 64mx64 -8 28 minimum row active to row active delay 15/16 ns 0f 10 29 minimum ras to cas delay 20 ns 14 30 minimum ras pulse width 45 ns 2d 32 31 module bank density (per bank) 256 mb 40 32 sdram input setup time 2 ns 15 20 33 sdram input hold time 1 ns 08 10 34 sdram data input setup time 2 ns 15 20 35 sdram data input hold time 1 ns 08 10 36-61 superset information ff 62 spd revision revision 1.2 12 63 checksum for bytes 0 - 62 37 9a 64- 125 manufactures?s information (optional) xx 126 frequency specification pc100 64 127 details c7 128+ unused storage locations ff
hy s 64v64220 g bdl 144 pin so-dimm sdram modules infineon technologies 12 2002.01.25 package outlines 512 mbyte so-dimm module package (jedec mo-190) (144 pin, dual read-out, single in-line memory module) note: all tolerances according to jedec standard 67.6 63.6 29.21 (3.3) 23.2 3.8 max. 1 20 (3.7) 1 1.8 4 6 59 61 143 32.8 2.5 4.6 26062 144 1.5 4 24.5 l-dim-144-12 2.55 0.25 0.8 detail of contacts 0.6 detail of chamfer 0.2 - 0.15 0.2 - 0.15 0.15 0.1 0.15 heat spreader
hys64v64220gbdl 144 pin so-dimm sdram modules infineon technologies 13 2002.01.25 rev changes: 6.7.200 first version 512mbyte cob-so-dimm based on 256 mb (32m x 8) chips 27.7.2000 icc currents from the latest 256m s17 datasheet 8.8.2000 icc6 changed from 12 to 14 ma (after the component datasheet changed from 1.5 to 1.7 ma) 6.09.2001 scr: absolute maximum ratings table added drawing with heat spreader adder to the package outline section 13.12.2001 product released for production datasheet changed from target to preliminary 2002-01-25 datasheet status changed from preliminary to final 2002-01-29 editorial changes on pages 1, 4, and 5 2002-01-29 page 12: changed module height from 28.96 to 29.21 (according to juergen hoegerl) and changed 256mbyte to 512mbyte 2002-01-29 editorial change: changed all vcc references to vdd 2002-01-29 page 8: changed tlz from 1 to 0 for -7.5 (remark georg eggers) 2002-01-29 page 8: changed refresh period from 4096 to 8192 (remark georg eggers) 2002-01-29 page 11: changed spd superset definition (bytes 36-61) from 00 to ff accor- ding to spd definition file on tm homepage (remark georg eggers)

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